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general description the MAX3580 fully integrated, direct-conversion tv tuner is designed for digital video broadcasting-terrestrial (dvb-t) applications. the integrated tuner covers a 170mhz to 230mhz input frequency range for the vhf-iii band and 470mhz to 878mhz for the uhf band. the MAX3580 direct-conversion tuner integrates an rf input switch and a multiband tracking filter, allowing low-power tuner-on-board applications without the cost and power-dissipation issues of dual-conversion tuner solutions. the zero-if architecture eliminates the need for saw filters by providing baseband i and q outputs directly to the demodulator. in addition, dc-offset can- cellation is implemented on-chip using a mixed-signal architecture to improve the second-order distortion per- formance and the dynamic range of the downstream digitizer and demodulator. the MAX3580 features dynamic gain control of more than 76db and a typical midband noise figure of 4.7db referred to the lna input. the vco architecture opti- mizes both in-band and wideband phase noise for ofdm applications where sensitivity to both 1khz phase noise and wideband phase noise related to strong adjacents can be a problem. the MAX3580 communicates using a 2-wire serial bus. the device operates from a typical +3.3v power supply and dissipates 650mw. the MAX3580 is available in a small 32-pin thin qfn package (5mm x 5mm) with an exposed paddle. electrical performance is guaranteed over the extended -40? to +85? temperature range. applications digital televisions digital terrestrial set-tops laptop televisions automotive televisions usb peripherals features 650mw power dissipation (at v cc = +3.3v) i and q baseband outputs eliminate all if-saw filters integrated rf tracking filters tunable baseband lowpass filters full-band vhf-iii and uhf tuning +38db digital acpr, +47db analog acpr low noise figure: 4.7db (typ) frac-n synthesizer for -90dbc/hz close-in phase noise baseband overload detector controls rf agc if desired +3.1v to +3.5v supply voltage range ultra-small, 5mm x 5mm thin qfn package MAX3580 direct-conversion tv tuner ________________________________________________________________ maxim integrated products 1 part temp range pin- package pkg code MAX3580etj+ -40? to +85? 32 tqfn-ep* t3255-5 MAX3580etj+t -40? to +85? 32 tqfn-ep* t3255-5 pin configuration/ functional diagram ordering information tracking filter gnd_tune ldo xe xb vcc_vco mux rfin2 addr2 lext vcc_syn rfin rf_agc scl sda bbi- bbq- bbq+ bb_agc bbi+ vcc_bb ref_buff vcc_rf ovld_det ind1 ind2 vcc_xtal vtune cp ovld_det gnd_lna gnd_cp gnd_pll n.c. top view 32 28 29 30 31 25 26 27 10 13 15 14 16 11 12 9 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 1 MAX3580 0 90 dac lo lo charge pump serial interface, control, and synthesizer 19-0611; rev 0; 7/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * ep = exposed paddle. + denotes lead-free package. t = tape-and-reel package. evaluation kit available
MAX3580 direct-conversion tv tuner 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (MAX3580 ev kit, v cc = +3.1v to +3.5v, gnd = 0v, bb_agc = rf_agc = +2.85v, rf input terminated into a 75 ? load, bbi_ and bbq_ are open, no input signal, vco active, registers set according to the specified default register conditions, t a = -40? to +85?, unless otherwise specified. typical values are at v cc = +3.3v, t a =+25?, unless otherwise specified.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.3v to +3.6v sda, scl, addr2, mux, ref_buff, bb_agc, rf_agc to gnd ................................-0.3v to +3.6v all other pins to gnd ..............................-0.3v to (+v cc + 0.3v) rf input power ...............................................................+10dbm operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +165? continuous power dissipation (t a = +70?) (derate 21.3mw/? above +70?) ..............................1702mw lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units supply voltage and current supply voltage v cc 3.1 3.5 v active 197 225 ma supply current i cc shutdown mode 200 ? rf_agc and bb_agc input bias current i agc v agc at +0.5v and +2.85v -50 +50 ? maximum gain 2.85 rf and baseband agc control voltage v agc minimum gain 0.5 v serial interface and mux output (scl, sda, mux) input logic-level low v il 0.3 x v cc v input logic-level high v ih 0.7 x v cc v input hysteresis 0.05 x v cc v sda, scl input current -10 +10 ? output logic-level low v ol sink current = 0.3ma 0.4 v output logic-level high v oh source current = 0.3ma v cc - 0.5 v caution! esd sensitive device
MAX3580 direct-conversion tv tuner _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units 170 230 operating frequency range f rf gain specification met across this frequency band 470 878 mhz rf_agc = bb_agc = +2.85v 74 overall voltage gain (note 2) rf_agc = bb_agc = +0.5v 26 db rf gain flatness w i thi n each v h f- iii and u h f b and ( n ote 10) -3 +3 db input return loss wor st case acr oss b and sel ected , 75 ? system 7 db 230mhz 5.4 470mhz 4.7 noise figure (dsb) (notes 3, 4) nf 858mhz 6.5 db broadband (notes 4, 5) 12 input 2nd-order intercept point iip2 br oad b and , rf_agc ad j usted for 49d b of g ai n > 26 dbm broadband (notes 4, 6) > -4 br oad b and , rf_agc ad j usted for 49d b of g ai n > 12 narrowband (notes 4, 7) -15 input 3rd-order intercept point iip3 narrowband, rf_agc adjusted for 49db of gain (note 7) 3 dbm p desired = -78dbm and converted to 3.75mhz, p tone 10mhz higher (note 4) -24 rf 1db desense rf_agc adjusted for 49db of gain, p desired = -55dbm -1 dbm rf i np ut r ang e of 170m h z to 960m h z ( n ote 8) -60 lo harmonic reception rf input range of 960mhz to 1400mhz > -40 dbc rf channel flatness 8mhz rf channel at baseband, tested at 169mhz and 469mhz -1 +1 db isolation dc to 30mhz, rf input to baseband output, relative to desired channel > 60 dbc i/q phase error at 1mhz -3 +3 d eg r ees quadrature accuracy i/q amplitude error at 1mhz -1.5 +1.5 db 50mhz to 470mhz -50 -20 470mhz to 878mhz -50 -35 spurious at the rf input (note 3) 878mhz to 1732mhz < -50 -20 dbmv at 1khz to 10khz (note 3) -80 -90 at 100khz (note 3) -94 -107 phase noise (single-sideband, closed loop) n at 1mhz -130 dbc/hz ac electrical characteristics (MAX3580 ev kit, v cc = +3.1v to +3.5v, gnd = 0v. rf_agc = bb_agc = +2.85v, rf input terminated into a 75 ? load, bbi_ and bbq_ loaded by r l greater than 2k ? and c l less than 10pf, vco active, registers are set according to the recommended default register conditions, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted.) (note 1)
MAX3580 direct-conversion tv tuner 4 _______________________________________________________________________________________ ac electrical characteristics (continued) (MAX3580 ev kit, v cc = +3.1v to +3.5v, gnd = 0v. rf_agc = bb_agc = +2.85v, rf input terminated into a 75 ? load, bbi_ and bbq_ loaded by r l greater than 2k ? and c l less than 10pf, vco active, registers are set according to the recommended default register conditions, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units sigma-delta fractional-n synthesizer reference oscillator frequency f ref 4 27 mhz input impedance z in 10 k ? voltage gain 30 v/v output impedance z out 15 ? buffered output 10k ? || 10pf load 0.7 v p-p dividers rf n divider ratio 5 251 rf r divider ratio 1 2 fractional-n resolution 20 bits lo phase detector and charge pump phase-detector frequency 4 27 mhz gain = 0 600 charge-pump current i cp gain = 1 1200 ? charge-pump tri-state current -10 +10 ? charge-pump compliance range charge-pump positive to negative current matching of ?% 0.4 v cc - 0.4 v local oscillator tuning frequency range f osc tank frequency 2160 4400 mhz vco dividers 4 16 baseband stage nominal output voltage (note 2) 1 v p-p 1db output compression point p 1db differential voltage at 3mhz 1.6 2 v p-p output impedance differential 60 ? passband agc range bb_agc = 0.5v to 2.85v 30 50 db passband cutoff attenuation at 3.8mhz (uhf mode); at 3.325mhz (vhf mode) 2 5 db passband differential gain error 2mhz to 3.8mhz, i channel vs. q channel (uhf mode) -0.45 +0.45 db passband group delay from dc to 3.8mhz over any 1.1khz band (uhf mode) 5 ns group delay mismatch from 0.1mhz to 3.8mhz, i channel vs. q channel (uhf mode) (note 9) < 2 ns
MAX3580 direct-conversion tv tuner _______________________________________________________________________________________ 5 ac electrical characteristics (continued) (MAX3580 ev kit, v cc = +3.1v to +3.5v, gnd = 0v. rf_agc = bb_agc = +2.85v, rf input terminated into a 75 ? load, bbi_ and bbq_ loaded by r l greater than 2k ? and c l less than 10pf, vco active, registers are set according to the recommended default register conditions, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units at 5.25mhz (uhf mode) 23 at 4.75mhz (vhf mode) 23 at 13.25mhz (uhf mode) 63 at 11.75mhz (vhf mode) 62 rejection ratio at > 16.2mhz 84 db dc output voltage v cm common mode (note 11) 0.485 x v cc v dc output dc offset bb_agc = 2.85v -70 +70 mv baseband highpass cutoff programmable 20 to 200 hz agc gain slope bb_agc = 0.5v to 2.85v 14 35 db/v ratio of passband to stopband noise bb_agc = 2.85v, 10khz to 3.8mhz vs. 16.2mhz to 23.8mhz 15 db mixer overload detector (rssi) attack-point accuracy 5.25mhz test tone ? db attack-point increment 3-bit dac 1.5 db detector on, v out = 0.5v 0.3 ma detector output sink detector off, v out = 2.85v 5 ? detector gain 30 v/v detector response time < 200 ? 2-wire interface clock rate 400 khz note 1: min and max limits are guaranteed by test above t a = +25? and are guaranteed by design and characterization at t a = -40?. the default register settings are not production tested. load registers no sooner than 100? after power-up. note 2: the specified overall voltage gain is suitable to amplify -93dbm to -20dbm to 1v p-p at the baseband output. note 3: guaranteed by design characterization over the specified operating conditions. not production tested. note 4: bb_agc adjusted for gain = 72db with rf_agc at 2.85v. note 5: two tones at a) 230mhz and 431mhz with im measured at 201mhz and b) 230mhz and 701mhz with im measured at 471mhz. note 6: two tones at 499mhz and 689mhz with im measured at 879mhz. note 7: im3 measured with two tones within the adjacent channel. production tested at 72db of gain with two tones at a) 205.75mhz and 210.5mhz with im measured at 201mhz and b) 475.25mhz and 479.5mhz with im measured at 471mhz. production tested at 49db of gain with two tones at 475.25mhz and 479.5mhz with im measured at 471mhz. note 8: measured at rf = 171mhz with harmonics at 511mhz (3rd harmonic) and 851mhz (5th harmonic). note 9: delay of 2ns equal 2.74 phase error. note 10: uhf rolloff of 4db in addition to gain flatness specification. note 11: production tested at v cc = +3.5v to limits of 1.7v ?.1v.
MAX3580 direct-conversion tv tuner 6 _______________________________________________________________________________________ test scenario comments spec minimum MAX3580 typical mbrai s2 immunity/acpr for n ? adjacent ch. 29db 40db mbrai s2 immunity/acpr n ? alternate ch. 40db 43db mbrai l3 li near ity/cr ossm od . w i th n +2 and n +4 ch. 40db 47db nordig 16 qam 2/3 s ensi ti vi ty at channel 21 ( 470 m h z) -84.1dbm -85.1dbm nordig qpsk 1/2 sensitivity at channel 42 (642 mhz) -92.1dbm -94.8dbm nordig 64 qam 7/8 sensitivity at channel 59 (778 mhz) -74.7dbm -76dbm performance to standards the following is selected overall performance data for the MAX3580 + digital demod ulator. table 1 shows the typical overall performance as mea- sured using the MAX3580 and one current production dvb-t demodulator. this reference design is available in nim card form factor upon request. mbrai refers to standard mbrai 04-102 iec 62002-1 available from www.ansi.org. nordig refers to standard unified 1.0.2 available from www.nordig.org. modulation of wanted and interfering channel(s) is 8k mode, 16 qam, c/r = 3/4, gi = 1/4, sensitivity or immunity reference bit error rate is 2 x 10e-4, unless stated otherwise. table 1. selected typical mbrai and nordig performance
MAX3580 direct-conversion tv tuner _______________________________________________________________________________________ 7 70 80 100 90 110 150 170 180 190 200 160 210 220 230 240 250 vhf-iii band voltage gain vs. frequency MAX3580 toc01 frequency (mhz) gain (db) t a = +25 c t a = 0 c t a = +85 c t a = +55 c 70 80 100 90 110 450 550 600 650 700 500 750 800 850 900 uhf band voltage gain vs. frequency MAX3580 toc02 frequency (mhz) gain (db) t a = +25 c t a = 0 c t a = +85 c t a = +55 c 10 40 30 20 50 60 70 80 90 100 110 01.0 0.5 1.5 2.0 2.5 3.0 voltage gain vs. rf_agc control voltage MAX3580 toc03 rf_agc control voltage (v) gain (db) t a = +25 c, +55 c t a = -40 c t a = +85 c bb_agc = 2.85v -120 -100 -110 -80 -90 -60 -70 -50 phase noise vs. offset frequency MAX3580 toc04 offset frequency (khz) phase noise (dbm/hz) 0.1 1 10 100 1000 620mhz 220mhz noise figure vs. vhf frequency frequency (mhz) noise figure (db) MAX3580 toc05 150 175 200 225 250 0 5 10 15 20 t a = -40 c t a = +25 c t a = +55 c t a = +85 c 0 5 15 10 20 450 550 600 650 700 500 750 800 850 900 noise figure vs. uhf frequency MAX3580 toc06 frequency (mhz) noise figure (db) t a = +25 c t a = -40 c t a = +85 c t a = +55 c typical operating characteristics (typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted.) 0 10 5 20 15 25 30 vhf mode noise figure vs. voltage gain MAX3580 toc07 voltage gain (db) noise figure (db) 60 70 75 65 80 85 90 t a = +25 c, +55 c t a = -40 c t a = +85 c f rf = 220mhz bb_agc = 2.85v
MAX3580 direct-conversion tv tuner 8 _______________________________________________________________________________________ 0 10 5 20 15 25 30 uhf mode noise figure vs. voltage gain MAX3580 toc08 voltage gain (db) noise figure (db) 60 70 75 65 80 85 90 t a = +25 c t a = +55 c t a = -40 c t a = +85 c f rf = 620mhz bb_agc = 2.85v 10 40 30 20 50 60 70 80 90 100 110 01.0 0.5 1.5 2.0 2.5 3.0 voltage gain vs. bb_agc control voltage MAX3580 toc09 bb_agc control voltage (v) gain (db) t a = +25 c, +55 c t a = -40 c t a = +85 c rf_agc = 2.85v baseband filter rejection ratio frequency (mhz) rejection ratio (db) MAX3580 toc10 0 5 10 15 20 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 vhf input uhf input noise limited -50 -5 -45 -40 -35 -30 -25 -20 -15 -10 0 5 normalized baseband frequency response MAX3580 toc11 frequency (mhz) gain (db) 02 1345 t a = +25 c t a = 0 c t a = +85 c bb_bw<3:0> = "1011" 8mhz channel mode -50 -5 -45 -40 -35 -30 -25 -20 -15 -10 0 5 normalized baseband frequency response MAX3580 toc12 frequency (mhz) gain (db) 02 1345 t a = +25 c t a = 0 c t a = +85 c bb_bw<3:0> = "1001" 7mhz channel mode -50 -5 -45 -40 -35 -30 -25 -20 -15 -10 0 5 normalized baseband frequency response MAX3580 toc13 frequency (hz) gain (db) 010 5152025 t a = +25 c t a = 0 c t a = +85 c bb_bw<3:0> = "1011" 8mhz channel mode normalized baseband frequency response MAX3580 toc14 frequency (mhz) gain (db) 0 5 10 15 20 25 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 t a = +25 c t a = +85 c t a = 0 c bb_bw <3:0> = "1001" 7mhz channel mode typical operating characteristics (continued) (typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted.)
MAX3580 direct-conversion tv tuner _______________________________________________________________________________________ 9 -45 -55 -65 -75 020 10 30 40 50 stopband noise vs. frequency MAX3580 tpc15 frequency (mhz) stopband noise (dbm) bb_bw <3:0> = "1011" 8mhz channel mode bb_bw <3:0> = "1001" 7mhz channel mode 0 10 5 20 15 25 30 vhf mode noise figure vs. bb_agc voltage MAX3580 toc16 bb_agc voltage (v) noise figure (db) 0 1.0 1.5 0.5 2.0 2.5 3.0 t a = +25 c t a = +55 c t a = -40 c t a = +85 c 220mhz rf_agc = 2.85v 0 10 5 20 15 25 30 uhf mode noise figure vs. bb_agc voltage MAX3580 toc17 bb_agc voltage (v) noise figure (db) 0 1.0 1.5 0.5 2.0 2.5 3.0 620mhz rf_agc = 2.85v t a = +25 c t a = -40 c t a = +55 c t a = +85 c 0 10 5 15 30 35 25 20 40 100 300 400 500 600 200 700 800 900 1000 rf port-to-port isolation MAX3580 toc18 frequency (mhz) gain (db) rfin2 to rfin rfin to rfin2 4 3 2 1 0 -60 -30 -50 -40 -20 -10 0 power-detector output voltage vs. rf input power MAX3580 tpc19 rf input power (dbm) power-detector output voltage (v) 10k ? pullup to 3.0v "111" "000" 0 -5 -10 -15 450 675 525 600 750 825 900 rf input return loss vs. uhf frequency MAX3580 toc20 uhf frequency (mhz) return loss (db) zo = 75 ? typical operating characteristics (continued) (typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted.) 0 -5 -10 -15 -20 150 200 175 225 250 rf input return loss vs. vhf frequency MAX3580 toc21 vhf frequency (mhz) return loss (db) zo = 75 ? 200 195 190 185 3.0 3.3 3.1 3.2 3.4 3.5 3.6 supply current vs. supply voltage MAX3580 toc22 v cc (v) i cc (ma) t a = +55 c t a = +85 c t a = -40 c t a = 0 c t a = +25 c
MAX3580 direct-conversion tv tuner 10 ______________________________________________________________________________________ pin description pin name function 1 sda serial-data input line. requires a pullup resistor to v cc . 2 scl serial-clock input. requires a pullup resistor to v cc . 3 rfin2 second rf input 4 rfin first rf input 5 addr2 address line. sets the 3rd lsb of the device address. connect to ground to set for ??or v cc to set for ?. 6 gnd_lna not internally connected. connect to ground. 7 vcc_rf dc supply for rf lna. connect as close as possible a 100pf capacitor from this pin to gnd. 8 lext external bias inductor. connect to v cc with a 270nh inductor. 9 rf_agc gain control input for rf vga. 10 ind1 vhf inductor pin 1. keep traces to inductor as short as possible. 11 ind2 vhf inductor pin 2. keep traces to inductor as short as possible. 12 n.c. no connection 13 ovld_det overload detector output. connect a 10k ? pullup resistor to v cc and a rc network to rf_agc. 14 vcc_bb d c s up p l y for baseb and fi l ter . c onnect as cl ose as p ossi b l e a 10nf cap aci tor fr om thi s p i n to g r ound . 15 bbq- quadrature inverted baseband output 16 bbq+ quadrature noninverted baseband output 17 bbi- in-phase, inverted baseband output 18 bbi+ in-phase, noninverted baseband output 19 bb_agc gain control input for baseband vgas 20 vcc_vco dc supply for the vco. connect as close as possible a 100pf capacitor from this pin to ground. 21 vtune vco tuning voltage input. connect the pll loop filter output directly to this pin. 22 gnd_tune ground reference for the tuning voltage. connect to ground of the loop filter. 23 ldo vco ldo output. connect a 0.1? capacitor to ground. 24 cp charge-pump output. connect the charge-pump output to the pll loop filter input. 25 gnd_cp ground for the charge pump 26 vcc_syn dc supply for synthesizer and serial-interface control. connect as close as possible a 10nf capacitor from this pin to ground. 27 gnd_pll ground for the pll 28 mux multiplex output line. can be used as a pll lock-detector output. 29 ref_buff buffered output of reference oscillator 30 vcc_xtal d c s up p l y for refer ence osci l l ator . c onnect as cl ose as p ossi b l e a 10nf cap aci tor fr om thi s p i n to g r ound . 31 xb reference input. connect to a parallel resonant mode xtal through a load-matching capacitor, or can also be used as a reference clock input pin. 32 xe reference oscillator feedback. connect to a capacitive divider when used in self-oscillating mode. ep ep exposed paddle. solder to the board? ground plane to achieve the lowest possible impedance path.
MAX3580 direct-conversion tv tuner ______________________________________________________________________________________ 11 typical application circuit tracking filter gnd_tune ldo xe xb vcc_vco v cc mux rfin2 addr2 lext vcc_syn v cc v cc rfin rf_agc scl sda bbi- bbq- bbq+ bb_agc bbi+ vcc_bb ref_buff vcc_rf ovld_det ovld_det q channel i channel ind1 ind2 vcc_xtal vtune cp ovld_det gnd_lna gnd_cp gnd_pll n.c. 32 28 29 30 31 25 26 27 10 13 15 14 16 11 12 9 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 1 MAX3580 0 90 dac lo lo charge pump serial interface, control, and synthesizer v cc v cc v cc
MAX3580 direct-conversion tv tuner 12 ______________________________________________________________________________________ detailed description programmable registers the MAX3580 includes thirteen write/read registers and three read-only registers. see table 2 for register con- figuration and the register description section. the register configuration of table 2 shows each bit name and the bit usage information for all registers. ? labeled under each bit name indicates that the bit value is user defined to meet specific application requirements. a ??or ??indicates that the bit must be set to the defined ??or ??value for proper operation. operation is not tested or guaranteed if these bits are programmed to other values and is only for factory/bench evaluation. for field use, always program to the defined operational state. note that all registers must be written after and no earlier than 100? after device power-up. table 2. register configuration 8-bit data register settings register address d7 d6 d5 d4 d3 d2 d1 d0 operation defined default settings (por) register name 0x00 n7 u n6 u n5 u n4 u n3 u n2 u n1 u n0 u h17 n-divider integer 0x01 mp 0 li1 0 li0 0 int u f19 u f18 u f17 u f16 u h18 n-divider frac2 0x02 f15 u f14 u f13 u f12 u f11 u f10 u f9 u f8 u h00 n-divider frac1 0x03 f7 u f6 u f5 u f4 u f3 u f2 u f1 u f0 u h00 n-divider frac0 0x04 tfs<7> u tfs<6> u tfs<5> u tfs<4> u tfs<3> u tfs<2> u tfs<1> u tfs<0> u ?db tracking filter series caps 0x05 vco_div1 u vco_div0 u rfs u tf_bs u tfp<3> u tfp<2> u tfp<1> u tfp<0> u h7c tracking filter parallel cap 0x06 rdiv u icp u cps u adly1 0 adly0 1 lf_div2 u lf_div1 u lf_div0 u h0a pll configuration 0x07 cp_tst2 0 cp_tst1 0 cp_tst0 0 x 0 turbo 1 ld_mux2 u ld_mux1 u ld_mux0 u h08 test functions 0x08 x 0 shdn_bg u shdn_pd u shdn_ref u shdn_syn u shdn_mx u shdn_bb u shdn_rf u h00 shutdown control 0x09 vco1 u vco0 u bs2 u bs1 u bs0 u vas 1 adl 0 ade 0 hc0 vco control 0x0a bb_bw3 u bb_bw2 u bb_bw1 u bb_bw0 u x 0 pd_th2 u pd_th1 u pd+th0 u h87 baseband control 0x0b bb_bia 0 dc_dac8 0 dc_mo1 1 dc_mo0 1 dc_sp1 1 dc_sp0 0 dc_th1 0 dc_th0 0 h38 h40 dc offset control 0x0c dc_dac7 0 dc_dac6 0 dc_dac5 0 dc_dac4 0 dc_dac3 0 dc_dac2 0 dc_dac1 0 dc_dac0 0 h00 h00 dc offset dac 0x0d x 0 fuse_th 0 x 0 wr 0 tfa<3> u tfa<2> u tfa<1> u tfa<0> u h00 rom table address 0x0e tfd<7> 0 tfd<6> 0 tfd<5> 0 tfd<4> 0 tfd<3> 0 tfd<2> 0 tfd<1> 0 tfd<0> 0 h00 h00 rom table fuse data 0x0f x 0 x 0 x 0 x 0 mx_hr<3> 0 mx_hr<2> 0 mx_hr<1> 0 mx_hr<0> 0 h00 h00 mixer harmonic rejection 0x10 tfr<7> tfr<6> tfr<5> tfr<4> tfr<3> tfr<2> tfr<1> tfr<0> n/a n/a rom table data read back 0x11 por vasa vase ld dc_lo dc_hi gkt pd_ovld n/a n/a chip status read back 0x12 vco1a vco0a bs2a bs1a bs0a adc2 adc1 adc0 n/a n/a autotuner read back
MAX3580 direct-conversion tv tuner ______________________________________________________________________________________ 13 register descriptions n-divider integer (register address 0x00) n<7:0>: vco integer-n divider ratio n-divider frac2 (register address 0x01) mp: minimum cp pulse width. always set to 0 (factory use only). li1, li0; cp linearity control. always set to 00 (factory use only). int: integer mode on/off. set to 0 for normal operation. f<19:16>: msb of main divider fractional divide ratio n-divider frac1, frac0 (register address 0x02, 0x03) f<15:0> 16 lsb of main divider fractional divide ratio tracking filter series capacitor (register address 0x04) tfs<7:4>: tracking filter parallel capacitor. tfs<3:0>: tracking filter series capacitor. see the rf tracking filter description in the applications information section. tracking filter parallel capacitor and vco control (register address 0x05) vco_div1, vco_div0: vco post divider 00 = divide by 4 use for rf frequencies of 540 to 868 mhz 01 = divide by 8 use for rf frequencies of 470 to 550 mhz 10 = divide by 16 use for rf frequencies of 170 to 230 mhz 11 = divide by 32 is not used rfs: rf input select 0 = rfin2 selected 1 = rfin selected tf_bs: tracking filter band select 1 = vhf band 0 = uhf band tfp<4:0>: tracking filter shunt capacitor see the rf tracking filter description in the applications information section. pll configuration (register address 0x06) lf_div2, lf_div1, lf_div0: prescaler for internal low frequency clocks 000 - 110 = divided by 8 to 14 for ref crystal fre- quencies of 15mhz to 28mhz 111 = divide by 2 for ref crystal frequencies of 4mhz adly1, adly0: vco autotuner delay selection cps: charge-pump current mode 0 = controlled by icp bit 1 = controlled by vco autotuner icp: charge-pump current 0 = 600? 1 = 1200? rdiv: pll reference divider ratio 0 = divide by 1 1 = divide by 2 test functions (register address 0x07) cp_tst<2:0>: charge-pump test modes 000 = normal operation 100 = low impedance* 101 = source 110 = sink 111 = high impedance ld_mux: lock-detector mode 000 = normal operation: high = pll locked, low = unlocked 001 = monitor n-divider output, post-divided by 2 010 = monitor r-divider output* 011 = modulator test vector output (factory use only) 1xx = bias current trim (factory use only) * not production tested.
MAX3580 direct-conversion tv tuner 14 ______________________________________________________________________________________ shutdown control (register address 0x08) shdn_bg: main bandgap 0 = enabled 1 = disabled the main bandgap can and will be shut down once all other blocks are shut down (i.e., all bits in this shutdown register and bits vco_ in the vco control register and bits dc_mo_ in the dc offset control register are shut down). shdn_pd: baseband power detector 0 = enabled 1 = disabled shdn_rf: rf lna/vga: 0 = enabled 1 = disabled shdn_mix: i/q mixer and lo drivers 0 = enabled 1 = disabled shdn_bb: baseband filters and vga 0 = enabled 1 = disabled shdn_syn: fractional pll 0 = enabled 1 = disabled shdn_ref: controls the crystal oscillator buffered output 0 = enabled 1 = disabled the xtal oscillator activation results from the shdn_syn, shdn_ref bits: if either one is on, the xtal oscillator runs. the xtal oscillator is shut down only if both bits are off. vco control (register address 0x09) vco<1:0>: selects 1 of 3 vco bands. 00 turns off vco block completely. bs<2:0>: selects 1 of 8 vco sub-bands vas: vco band autoselect 0 = vco band select controlled by bits vco<1:0> 1 = controlled by autotuner adl: vco adc latch enable bit 1 = latches adc value 0 = default ade: enable vco tune voltage dac read 1 = enables adc read 0 = default baseband control (register address 0x0a) pd_th<2:0>: detection threshold for baseband power detector bb_bw<3:0>: baseband filter bandwidth. optimum values for 7mhz and 8mhz wide rf channels can be taken from the rom table. dc offset control (register address 0x0b) dc_th<1:0>: dc offset correction thresholds. keeps output within: 00 = output within ?.55v of balanced state 11 = output within ?.75v of balanced state dc_sp<1:0>: dc offset correction speed (or highpass corner frequency). 11 = fast (~500hz) 01 = slow (~20hz) 00 = off/hold dac values dc_mo<1:0>: mode of operation 00 = off 10/01 = sets i/q channel dacs direct from register 11 = normal operation dc_dac<8>: msb for dc offset dac bb_bia: baseband filter op-amp bias settings 0 = low 1 = high * not production tested.
MAX3580 direct-conversion tv tuner ______________________________________________________________________________________ 15 dc offset dac (register address 0x0c) dc_dac<7:0>: value to program to i/q dc offset dac. note that the msb is located in the previous register. tracking filter rom address (register address 0x0d) tfa<3:0>: tracking filter rom address. see table 3. tracking filter write data (register address 0x0e) tfd<7:0>: tracking filter data for rom tracking filter rom read back (read only) (register address 0x10) tfr<7:0>: tracking filter rom data read back status (read only, for factory use only) (register address 0x11) por: power-on reset 0 = power has not been reset since the last read. 1 = power has been reset since the last read. gets reset after reading back address 8?0c. vasa, vase: vco autotuner status* ld: pll lock detector 0 = pll unlocked 1 = pll locked dc_hi: dc offset correction detected positive signal excursion in either i or q channel* dc_lo: dc offset correction detected negative signal excursions in either i or q channel* pd_ovld: baseband power detector 0 = baseband signal below threshold 1 = baseband signal above threshold autotuner read back (read only, for factory use only) (register address 0x12) vcoa<1:0> vco tank selected by autotuner* bsa<1:0> sub-band vco selected by autotuner* adc<2:0> vco tank voltage adc* table 3. MAX3580 fuse table byte 7 6543 2 1 0 description 00 unused bias bias trim 01 vhf (200mhz) parallel cap vhf (200mhz) series cap vhf high series cap 02 unused vhf (200mhz) shunt cap vhf shunt cap 03 uhf low (470mhz) parallel cap uhf low (470mhz) series cap uhf low series cap low 04 uhf high (860mhz) shunt cap uhf low (470mhz) shunt cap uhfhigh/low parallel cap 05 uhf high (860mhz) parallel cap uhf high (860mhz) series cap uhf high series cap 06 baseband filter uhf (8mhz) coefficient. baseband filter vhf (7mhz) coefficient. bb filter bandwidth 07 x x x x x x x ro read only * not production tested.
MAX3580 direct-conversion tv tuner 16 ______________________________________________________________________________________ to read back fuses important notice: when reading other addresses than 8?00 (the system trim bits), it is possible that the data going to the bias cells will be disturbed due to the architecture of the fuse bank. this means the bias cur- rent could change while reading back fuse data. 1) write 8?xx to tfa. xx is the address of the fuse col- umn you want to read. 2) read 8?xx from tfr. tfr is the tracking filter read register. 3) repeat steps 1 and 2 for other addresses. 2-wire serial interface the MAX3580 uses a 2-wire i 2 c*-compatible serial interface consisting of a serial-data line (sda) and a serial-clock line (scl). the serial interface allows com- munication between the MAX3580 and the master at clock frequencies up to 400khz. the master initiates a data transfer on the bus and generates the scl signal to permit data transfer. the MAX3580 behaves as slave devices that transfer and receive data to and from the master. pull sda and scl high with external pullup resistors (1k ? or greater) for proper bus operation. one bit is transferred during each scl clock cycle. a minimum of nine clock cycles are required to transfer a byte in or out of the MAX3580 (8 bits and an ack/nack). the data on sda must remain stable during the high peri- od of the scl clock pulse. changes in sda while scl is high and stable are considered control signals (see the start and stop conditions section). both sda and scl remain high when the bus is not busy. start and stop conditions the master initiates a transmission with a start condi- tion (s), which is a high-to-low transition on sda while scl is high. the master terminates a transmission with a stop condition (p), which is a low-to-high transition on sda while scl is high. acknowledge and not-acknowledge conditions data transfers are framed with an acknowledge bit (ack) or a not-acknowledge bit (nack). both the mas- ter and the MAX3580 (slave) generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. to generate a not-acknowledge condition, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves sda high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuc- cessful data transfer, the bus master must reattempt communication at a later time. slave address the MAX3580 has a 7-bit slave address that must be sent to the device following a start condition to initi- ate communication. the slave address is determined by the state of the addr2 pin and is equal to 11000[addr2]0 (see table 4). the eighth bit (r/ w ) fol- lowing the 7-bit address determines whether a read or write operation will occur. the MAX3580 continuously awaits a start condition followed by its slave address. when the device recog- nizes its slave address, it acknowledges by pulling the sda line low for one clock period; it is ready to accept or send data depending on the r/ w bit (figure 1). *purchase of i 2 c components of maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. table 4. address configuration address (write/read) addr2 c0/c1 hex 0 c4/c5 hex 1 scl sda 123456789 s11000 0r/ wack slave address addr2 figure 1. MAX3580 slave address byte
MAX3580 direct-conversion tv tuner ______________________________________________________________________________________ 17 write cycle when addressed with a write command, the MAX3580 allows the master to write to a single register or to multi- ple successive registers. a write cycle begins with the bus master issuing a start condition followed by the seven slave address bits and a write bit (r/ w = 0). the MAX3580 issues an ack if the slave address byte is successfully received. the bus master must then send to the slave the address of the first register it wishes to write to. if the slave acknowledges the address, the master can then write one byte to the register at the specified address. data is written beginning with the most significant bit. the MAX3580 again issues an ack if the data is suc- cessfully written to the register. the master can contin- ue to write data to the successive internal registers with the MAX3580 acknowledging each successful transfer, or it can terminate transmission by issuing a stop con- dition. the write cycle does not terminate until the mas- ter issues a stop condition. figure 2 illustrates an example in which registers 0 through 2 are written with 0x0e, 0xd8, and 0xe1, respectively. read cycle when addressed with a read command, the MAX3580 allows the master to read back a single register or mul- tiple successive registers. a read cycle begins with the bus master issuing a start condition followed by the 7 slave address bits and a write bit (r/ w = 0). the MAX3580 issues an ack if the slave address byte is successfully received. the bus master must then send the address of the first register it wishes to read. the slave acknowledges the address. then a start condition is issued by the master, fol- lowed by the 7 slave address bits and a read bit (r/ w = 1). the MAX3580 issues an ack if the slave address byte is successfully received. the MAX3580 starts send- ing data msb first with each scl clock cycle. at the 9th clock cycle, the master can issue an ack, and continue to read successive registers, or the master terminate the transmission by issuing a nack. the read cycle does not terminate until the master issues a stop condition. figure 3 illustrates an example in which registers 0 through 2 are read back. start write device address r/ w 1100000 write register address 0x00 0 ack ack write data to register 0x00 0x0e ack write data to register 0x01 0xd8 ack write data to register 0x02 0xe1 ack stop figure 2. example: write registers 0 through 2 with 0x0e, 0xd8 and 0xe1, respectively. s t a r t s t a r t a c k a c k a c k a c k a c k n a c k s t o p device address device address reg 00 data reg 01 data reg 02 data register address r/ w 11000000 00000000 11000000 xxxxxxxx xxxxxxxx xxxxxxxx 01 r/ w figure 3. example: receive data from read registers.
MAX3580 direct-conversion tv tuner 18 ______________________________________________________________________________________ applications information band selection the MAX3580 is designed to be suitable for operation in the 170mhz to 230mhz vhf-iii band and in the 470mhz to 878mhz uhf band. rf inputs a switch selects either rfin or rfin2 as the input to the single-ended broadband matched lna. this switch is programmed through the rfs bit (bit 5) of register 0x05. the lna provides a continuous gain control range of typically 50db before the signal is downconverted. for optimal matching above 600mhz, add a 5nh to 6nh inductor in series with a capacitor at either of the rf input. application note: front end diplexer filter for MAX3580 is available, detailing the implementation of a uhf and vhf simple diplexer. this simple diplexerl improves strong-signal-handling capabilities of the MAX3580. dc-offset cancellation the MAX3580 features an on-chip fast-settling, dc-off- set cancellation circuitry that requires no off-chip com- ponents. note that the offset correction circuit is not enabled when the device is powered up. to enable the offset correction circuit, program the dc-offset control register to the recommended default setting. when active, the offset correction circuit creates a highpass characteristic in the signal path with a typical corner frequency of 200hz, and the residual dc offset can be as high as ?0mv. gain control the MAX3580 features two vga circuits that can be used to achieve the optimum snr. the two circuits can be driven independently by the baseband controller, which allows balancing the gain based on snr measure- ments in the digital demodulator. if only one gain control voltage can be provided by the digital demodulator, the rf vga is controlled by the baseband power detector of the MAX3580. see the baseband power detector sec- tion. in this operation mode, the baseband gain is set by an amplitude detector in the digital demodulator. baseband power detector the MAX3580 baseband power detector compares the total weighted receive input signal within approximately 2 channels of the wanted channel to a programmable threshold. this threshold can be programmed to differ- ent values with the pd_th<2:0> bits in the baseband control register. to close the rf gain control loop, connect the 300? control current sink of the power detector (pin ovld_det) to v cc with a 10k ? pullup resistor. the resulting voltage is fed with an rc lowpass to the rf_agc input. synthesizer loop filters a second-order lowpass loop filter is used to connect the pll to the rf local oscillator. a loop filter bandwidth of 30khz is optimal for fractional pll spurs and integrat- ed lo phase noise. refer to the ev kit data sheet for the recommended loop-filter component values. crystal-oscillator interface the MAX3580 reference oscillator circuitry can be used either as a high-impedance reference input driven by an external source, or be configured as a crystal oscil- lator. in the latter case, the resulting frequency can be used to drive the digital demodulator chip through the buffered reference output of the MAX3580. when using an external reference oscillator, drive the xb input through an ac-coupling capacitor with amplitude of approximately 1.5v p-p , and leave xe unconnected. note that the phase noise of the external reference needs to exceed -140dbc/hz at offsets of 1khz to 100khz. when connecting directly to a crystal, see the typical application circuit for the required topology. for particular capacitor values, possible changes to accommodate for different crystal frequencies, crystal load-capacitance requirements, and crystal power-dis- sipation requirements, refer to the ev kit data sheet.
MAX3580 direct-conversion tv tuner ______________________________________________________________________________________ 19 rf tracking filter the MAX3580 utilizes two narrowband rf tracking filters, one for vhf and one for uhf. each filter is comprised of a fixed inductor and three digitally controlled variable capacitors named series, shunt, and parallel capacitors. the integrated rf tracking filters uses an external induc- tor between ind1 and ind2 pins to set the filter? center frequency. the inductor value must be 68nh ?% in order to achieve the corner frequency response. the vari- able capacitors are factory calibrated to this particular inductor value. the value of each capacitor is also set to compensate for process variation of each individual part and to receive the desired rf channel. the process variation is factory calibrated by determin- ing the best capacitor values for three discrete frequen- cies, which are stored in the on-chip rom table. upon power-up these values (6 bytes total) have to be read out of the MAX3580 rom table and stored in the micro- processor local memory. when tuning the MAX3580 to a given rx frequency, the correct capacitor value has to be calculated using the following linear formulas and written to the appropriate registers. this is in addition to programming the pll with the desired frequency. the formulas differ for vhf and uhf bands but are the same for all three capacitor values. since the factory calibration coefficients stored on the MAX3580 can dif- fer for each capacitor, the calculations have to be exe- cuted for all three capacitor values separately. vhf: capacitor = rom_value_vhf - (rx_frequency_in_mhz - 200mhz ) / 10mhz in other words, the capacitor values to be written to the max3550 decrease 1 count per 10mhz above 200mhz and increase accordingly below 200mhz. uhf: capacitor = rom_value_uhf_lo - (rom_value_uhf_lo - rom_value_uhf_hi) x (rx_frequency_in_mhz - 470mhz ) / 390mhz this means the capacitor values stored in the uhf_lo entries of the MAX3580 rom table are the correct values for 470mhz reception and the uhf_hi values for 860mhz reception. for any frequency in between, the capacitor values are obtained by a simple linear interpolation. note: when tuning to frequencies above 860mhz channel center frequency, do not use the formula above, but rather keep programming the tracking filter with the coefficients obtained for 860mhz. examples: assuming the MAX3580 rom table entries are c series vhf = 8, c series uhf_lo = 15, c series uhf_hi = 3 208mhz: c series = 8 - round ( ( 208-200 ) / 10 ) = 7 (floating point division, round to nearest integer after division) 8 - floor ( ( 208 - 200 + 5) / 10 ) = 7 (all calculations using signed integer values, truncate result of division) 677mhz: c series = 15 - round ( (15-3) x (677 - 470) / 390 ) = 9 (floating point division, round to nearest integer after division) 15 - floor ( ( ( 15-3) x (677-470) + 195 ) / 390 ) = 9 (all calculations using signed integer values, truncate result of division) power-supply layout to minimize coupling between different sections of the ic, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at the central v cc node. the v cc traces branch out from this node, with each trace going to separate v cc pins of the MAX3580. next to each v cc pin is a bypass capacitor with a low impedance to ground at the frequency of interest. use at least one via per bypass capacitor for a low-inductance ground connection. the three ground pins (gnd_pll, gnd_cp, gnd_tune) must be connected to the ground plane by separate via holes and must not be directly connect- ed to the exposed paddle. chip information process: bicmos
MAX3580 direct-conversion tv tuner 20 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps
MAX3580 direct-conversion tv tuner maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 21 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)

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